This application is a divisional application of U.S. patent application Ser. No. 08/801,819, filed on Feb. 14, 1997, now U.S. Pat. No. 6,060,385, which is incorporated herein by reference.
1. The Field of the Invention
The present invention relates to metallization methods in the manufacture of microelectronic semiconductor devices. More particularly the present invention relates to methods of making microelectronic semiconductor devices having up to three-level interconnect structures of conductive materials in which a single deposition process is used.
2. The Relevant Technology
After fabrication of microelectronic devices in and upon semi-conductive substrate assemblies, metallization of the circuitry is required to place the microelectronic devices in electrical communication one to another according to design. Prior art designs called for contacts, trenches, and superficial wires for metallization. These designs may require three or more separate depositions of conductive material in order to complete metallization of the design. Each layer of conductive material was made by the steps of depositing the conductive layer, depositing and patterning a photoresist or equivalent, and etching the conductive layer.
With multiple depositions of conductive material, usually composed of a metal or a doped polysilicon, various technical challenges and device characteristics arise. As semiconductor manufacturing advances from very large scale integration (VLSI) to ultra-large scale integration (ULSI), the devices on a semiconductor wafer shrink to sub-micron dimensions, and the circuit density increases to several million transistors per die. In order to accomplish the required high device packing density, progressively smaller feature sizes have been required. These reduced feature sizes include the width and spacing of interconnecting lines in the service geometry thereof, such as corners and edges.
As features become smaller, a process flow that requires multiple depositions tends to narrow the process window for error in misalignments. As such, a single misalignment in metallization can cause a significant yield reduction.
One technical obstacle in metallization line formation is depth-of-field limits in photolithography. Formation of metallization lines follows contact plug filling by deposition and patterning of a deposited metallization material. When a contact plug is formed in a contact hole, the metallization material that fills the contact hole may have an irregular surface immediately below the contact hole due to the filling thereof. The irregular surface of the metallization material has depth-of-field focusing problems due to a rough topography thereof. The rough topography can cause photolithographic steps to produce irregular metallization line widths, which in turn lead to unpredictable resistances along the metallization lines and unreliable device speeds.
Another technical obstacle is the inherent resistance in metal-to-metal interfaces between contacts and trenches, contacts and metallization lines, and trenches and metallization lines. This obstacle arises when disparate metals make up the contact and metallization line, or even when metals of the same composition are poorly interfaced. The process of forming contacts in semiconductors and the subsequent wiring of those contacts to form a completed integrated circuit conventionally comprises two steps.
The first step comprises forming an aluminum or tungsten plug within a contact hole by such methods as, for example, cold or hot deposition, cold-slow, or hot-fast force filling, or metal reflow of the contact hole. There are other methods of hole filling with aluminum known in the art. Tungsten plug hole filling comprises deposition of selected adhesional and barrier liner layers, followed by CVD of tungsten. The contact hole is usually defined within an insulation layer. Next, a planaizing step leaves the titanium or tungsten plug electrically isolated in the contact hole. The second deposition step comprises forming a metallization line over the plug, where the metallization line is usually composed of a material different from that of the plug.
The plug interface with the metallization line is problematic to electrical conduction because completely connected interface areas are difficult to achieve, particularly in dissimilar metals. Because resistance in electrical conduction is a function of cross-sectional area through the conductive body, a less than completely connected interface between contact or trench and metallization line causes a higher resistance than a completely connected interface. In addition to incomplete interface connections, filling a contact hole with aluminum requires high temperatures and pressures that may cause large or irregular grain structures to grow. Large or irregular grain structures resist flow and etchback, and do not conduct current as well as fine-grained structures.
Still other technical obstacles are electromigration and metal creep. These involve the transport of metal atoms along the direction of electron flow in the conductive lines, and can lead to failure of the conductive lines. These obstacles are discussed below in turn.
Aluminum-copper electromigration is well established in a structure with an aluminum-copper metallization line interfacing with a titanium or tungsten plug. The phenomenon occurs because copper diffusivity through titanium or tungsten is much lower than copper diffusivity through aluminum. Therefore, the copper is depleted from the area of the titanium or tungsten plug by the current flow, leading to failure at the interface between the titanium or tungsten plug and the aluminum-copper line.
Metal creep, on the other hand, occurs due to differences in the thermal coefficients of expansion between metals, insulators, and silicon materials. Differences in thermal coefficients of expansion can build up stresses in the metal interconnects, which can lead to migration of atoms from one area to another. This migration of atoms forms voids or vacancies in the metal interconnect which can cause an electrical failure.
The problems of cumulative misalignments and of electrical resistance at metal-metal interfaces with its several destructive effects, are to be avoided. What is needed is methods of making multi-level interconnect structures that overcome these problems.
The present invention comprises a method of forming a three-level interconnect metallization scheme for placing microelectronic devices in a circuit in electrical communication. The inventive method comprises forming a substrate assembly and depositing thereon a first dielectric layer. As used herein, a substrate assembly is one or more layers or structures upon a substrate. A second dielectric layer is then deposited over the first dielectric layer. The second dielectric layer is then patterned and etched twice. The first pattern and etch of the second dielectric layer is an anisotropic etch that forms contact corridors. By way of example, and not by way of limitation, a contact corridor can be a via. The second pattern and etch of the second dielectric layer forms one or more trenches. Preferably, one or more of the trenches will be formed directly above and contiguous to a corresponding contact corridor.
After trench formation, a filling step is performed. During the filling step, an electrically conductive material is deposited into the contact corridors and into the trenches so as to leave excess electrically conductive material above the contact corridors and trenches and upon the second dielectric layer. Additional steps, as a part of the filling step, may be taken to ensure a complete filling of the contact corridors and trenches. The excess electrically conductive material is situated directly above the contact corridors and trenches, thus forming a unitary integrated three-level interconnect.
After the single deposition step, but before the filling step, an optional antireflective coating is deposited to assist in a complete filling of the contact corridors and trenches. An optional planarization of the electrically conductive material can be carried out after the filling step.
After the filling step, either with or without the optional planarization of the electrical conductive material, a second optional antireflective coating is deposited to assist in reducing reflections that hinder subsequent photolithographic processing.
Finally, pattering and etching of the excess electrically conductive material is done. The remaining electrically conductive material in the contact corridors, the trenches, and above the second dielectric layer is formed into a single integral structure, the material of which is supplied to the substrate assembly in a single deposition step. The electrically conductive material in forming single integral structures in combinations of the contact corridors, trenches, and portions above the second dielectric layer each have a substantially constant electrical resistance from the top surface thereof to the bottom surface thereof. The substantially constant electrical resistance is due to the absence of metal-to-metal interfaces therein, which absence is inherent to the single deposition of the electrically conductive material.
These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.